Use of low-level hardware description languages (HDLs), like VHDL, has prevented the development of a software engineering discipline for hardware programming. Furthermore, the use of synthesized sequential C-like language has failed to deliver the performance and efficiency to replace HDL.
The psC language is a true high-level HDL designed to replace VHDL and Verilog.
The development or programs for FPGA is currently based on low level languages like VHDL and Verilog. These languages are hard to master, and their use has led to the creation of multiple add-on tools. For example, there are core generators to help in the design of simple counter, digital filters or video processing functions. There are also high-level-tools for fix-point and floating-point computations or system design. In addition, to simplify programmer's work, C-Like languages have been used to translate sequential algorithms and synthesize hardware.
Use of Low-Level Hardware Description Languages (HDL) has prevented the development of a software engineering discipline for hardware programming and C-like language synthesizers have failed to deliver the performance and efficiency to replace HDL.
A single High-Level Language spanning the whole design hierarchy from Register Transfer to complex parallel or sequential algorithms is required.
The psC language is a true "High-Level HDL" capable of replacing low-level languages.
To illustrate our point, let's have a look at computer programming. In the beginning, computers were programmed using assembly language. Programmers quickly realized they needed a simpler way.
A new generation of languages and tools has been invented: High-Level Languages and Compilers. These new tools enabled the design of more complex programs with new algorithms. These tools allowed exploration of the design space, and finally hit their limits. Then another generation was invented: Object Oriented Programming, and so on.
From this example, we can enumerate some criteria for the next generation of languages and tools.
A new generation of tools should also facilitate design:
And finally, adequate abstraction mechanisms must exist for:
The psC language supports a new abstraction mechanism that makes programming hardware easier. The main feature of psC is to abstract the clock and introduce an event-based control mechanism.
The programmer does not have to manage clock cycles, only events.
A High-Level Language is meant to replace a Low-Level Languages and facilitate programming. In addition, new HLL programs must be as efficient as the low level implementations. See what Bjarne Stroustrup, the inventor of the C++ language has to say about language design goals.
Have a look at the full article for insightful details.
Stroustrup answer gives us two basic requirements for the new language :
The question is : How to achieve it? Bjarne Stroustrup gives the answer:
The psC Language was designed with this objective in mind.
Therefore, the first question we should be asking ourselves is: What kind of machine is a FPGA? A FPGA is a parallel and synchronous machine. It is not a sequential machine. Therefore, if one wants to map language features on such a machine, the language execution model must be parallel and synchronous. Second, everything in an FPGA is organized as components with IO ports. The language must therefore support the component model and its hierarchical abstraction. Finally, all operations in a FPGA are based on a clock. Somehow, the language must keep this notion of steps.
As with low-level HDL, a psC program consists of interconnected components with IO ports. The execution model is "parallel and synchronous". Even if the programmer does not manage clock cycles, the execution is based on "steps" and is triggered by events transmitted between components.
A psC component consists of functions and memory elements: variables, ports and arrays.
As discussed in the previous section, the FPGA machine consists of components communicating using signals. In addition, execution on the FPGA is based on a clock and all states synchronously change with the clock in a sequence of steps. Here are the fundamental rules defining the new execution model of the synchronous and parallel paradigm.
These rules define the "Parallel and Synchronous Paradigm". Without a lengthy discussion, it can be observed how such paradigm maps directly on a FPGA machine. As a real FPGA, the execution of a psC program is identical to a synchronous sequential machine.
VHDL programmers might say: What's the difference since VHDL already supports synchronous sequential machine. The difference lays in the language implementation. For example, in sequential programming, the C++ language does the same thing as assembly language but differently, in a more abstract way.
This is the essence of the psC language: abstraction of the digital circuit world so programmers don't need any hardware knowledge.
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